Silicon Logic Engineering and Mentor Graphics Collaborate to Resolve Crucial Design Issues for Largest, Most Complex Chips
Proven Design Services, Emulation System Combination Reduces Risk of Costly Silicon Re-spins
EAU CLAIRE, Wis., and WILSONVILLE, Ore., Sept 15 /PRNewswire/ -- Silicon Logic Engineering (SLE) and Mentor Graphics Corp. today announced a business collaboration that speeds mission-critical design verification and dramatically reduces the risk of costly additional manufacturing operations due to undetected design errors.
Ideal for the networking and high-speed computing companies whose very complex ASIC (application specific integrated circuit) designs exceed the capabilities of other chip verification solutions, this collaboration unites SLE's proven design methodologies and Mentor's popular VStation(TM) emulation environment. VStation, which simulates the chip's functionality and performance within an electronic system, delivers 1,000 to 10,000 times performance increases over traditional software simulation approaches. SLE, who specializes in right-first-time, high-end ASIC and SOC (System On Chip) design services, has added VStation emulation solutions to SLE's proven and repeatable design process.
Undetected chip functionality and performance errors often result in additional manufacturing cycles called "respins" that require new mask sets which can cost $870,000 for 130nm designs and upwards of $1,500,000 for 90 nm designs. "As ASIC designs continue to grow in size and complexity, experienced teams are modifying methodologies and adding emulation tools to keep the ASIC approach a cost- and time-effective option," said Jordan Selburn, Principal Analyst for research firm iSuppli. "This trend needs to continue because the cost of pre-manufacturing verification can be an order of magnitude less than the cost of silicon respins."
"Ensuring that today's multi-million gate ASICs will work to specification is a serious bottleneck that can impact the ability to get exciting new electronic products to market," said Eric Selosse, vice president and general manager of the Mentor Emulation Division (MED). "The verification productivity and high-performance from the VStation emulator, harnessed by the experienced design engineers at SLE, will enable our high-end ASIC customers to reduce the risk of silicon respins and improve the quality of designs."
With roots in the supercomputer industry, SLE specializes in detecting possible functionality and performance errors early in the ASIC design cycle. SLE has delivered more than 30 high-gate count, high performance ASICs and system chips right-first-time to a variety of networking and computing systems customers. Mentor's VStation emulation system is now an integral part of SLE's complex ASIC design methodology that incorporates leading electronic design automation (EDA) products.
"We've been very impressed with the accuracy and performance of Mentor's VStation and are currently adding VStation emulation services for our customers who are pushing the ASIC design envelope," said Jeff West, president of SLE. "Adding Mentor's VStation emulation to our design services offering furthers SLE's ability to produce the 'right-first-time' ASIC designs that our customers expect."
About SLE
SLE specializes in right-first-time, leading edge, digital ASIC design services that address all aspects of complex ASIC development from concept to silicon. SLE's proven and repeatable Think Physical(TM) design process, tools, and semiconductor intellectual property reduce time-to-market and are provided by one of the most experienced VLSI design teams in the industry. Founded in 1996 by former Cray Research engineers, SLE is headquartered in Eau Claire, Wisconsin. For more information, visit us at http://www.siliconlogic.com/ .
About Mentor Graphics
Mentor Graphics Corporation (NASDAQ: MENT) is a world leader in electronic hardware and software design solutions, providing products, consulting services and award-winning support for the world's most successful electronics and semiconductor companies. Established in 1981, the company reported revenues over the last 12 months of about $600 million and employs approximately 3,500 people worldwide. Corporate headquarters are located at 8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777; Silicon Valley headquarters are located at 1001 Ridder Park Drive, San Jose, California 95131-2314. World Wide Web site: www.mentor.com .
Mentor Graphics is a registered trademark of Mentor Graphics Corporation. All other company or product names are the registered trademarks or trademarks of their respective owners.
CONTACT: Lynda Kaye of Mango Communications, +1-650-947-9876,
lynda@mangocommunications.com , or Anna Sizer of Silicon Logic Engineering,
Inc., +1-715-830-1200, anna@siliconlogic.com
Web site: http://www.siliconlogic.com/
http://www.mentor.com/
|
